1. Field of the Invention
The present invention relates generally to the field of microprocessor design and operation. In one aspect, the present invention relates to a fault tolerant memory for use in designing and debugging a CPU.
2. Description of the Related Art
Computer systems are constructed of many components, typically including one or more processors that are connected for access to one or more memory devices (such as RAM) and secondary storage devices (such as hard disks and optical discs). For example, FIG. 1 is a diagram illustrating a multiprocessor system 10 with multiple memories. Generally, a processor 1a connects to a system bus 12. Also connected to the system bus 12 is a memory (e.g., 14a). During processor operation, CPU 2 processes instructions and performs calculations. Data for the CPU operation is stored in and retrieved from memory using a memory controller 8 and cache memory, which holds recently or frequently used data or instructions for expedited retrieval by the CPU 2. Specifically, an L1 cache 4 connects to the CPU 2, followed by an L2 cache 6 connected to the L1 cache 4. The CPU 2 transfers information to the L2 cache 6 via the L1 cache 4.
As will be appreciated, there can be performance inter-dependencies between the various components of a computer system. For example, in systems where the L1 cache 4 transfers information using one line width (e.g., 32 bytes at a time) and the L2 cache 6 and the memory controller 8 transfer information using a different line width (e.g., 64 bytes at a time) to the system bus 12, the performance of the CPU 2 depends on the data merging or coalescing function provided by the L2 cache 6. This function may be implemented by including a plurality of cache lines in the L2 cache (e.g., each cache line 255 having a 64 byte capacity) for storing information between transfers.
This performance inter-dependence can adversely affect the design and performance of processor devices, particularly where the components are integrated on a single chip, since the initial silicon implementation of an integrated circuit often includes errors and bugs. In particular, if any of the components (such as the CPU 2, the L1 cache 4, or the L2 cache 6) fails to yield during manufacturing, the processor will not function. Such a failure can be caused by contaminants that are present during manufacture of the processor circuit, and can also be caused by bugs or errors that are present in the design or instruction set for the CPU 2. And as the circuit size, density and complexity increase, there are more opportunities for physical and circuit defects in the constructed integrated circuits. While the processor can be tested to identify and remove bugs or defects, such testing is impeded if it can not be determined what part of a complex integrated circuit is causing the defect. For example, if the L2 cache 6 is the only nonfunctioning portion of the processor, it is not possible to test the remaining portions of the processor during processor design because multiple bytes must coalesce within the cache. Subsequently, by not testing the processor, the design stage is delayed as processor manufacturers attempt to yield a processor with a functioning L2 cache 6.
Such delays can be substantial and can impede circuit design efforts. For example, conventional CPU pipeline debug operations can take up to a year or more to perform, but when a CPU is integrated on a single chip with additional circuitry that has its own complexities and potential for defects, the debug operations are further delayed while the additional circuitry is debugged or corrected. Thus, there is a need for a scheme which accelerates the design of a primary circuit (such as a CPU or microprocessor) and minimizes the design delay effects caused by the presence of errors or defects in a secondary circuitry (such as an on-board cache) that is associated with the primary circuit. There is also a need for accelerating the testing of a processor with a nonfunctioning coalescing cache to reduce the time and expense used in processor testing and manufacturing. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.